There are a number of conventional processes for packaging integrated circuits. One approach that is commonly referred to as “flip chip” packaging generally contemplates forming solder bumps (or other suitable contacts) directly on the face of an integrated circuit die. In some situations, the contacts are formed directly on I/O pads formed on the die, whereas in other situations the contacts are redistributed. The die is then typically attached to a substrate such as a printed circuit board or package substrate such that the die contacts directly connect to corresponding contacts on the substrate.
Some types of IC may be sensitive to light. That is, errors in IC operation may be introduced when the IC is exposed to certain light sources (e.g. infrared light). In many packaging approaches, an IC is encapsulated (typically by an opaque plastic material) or encased in a package that optically isolates the device. However, in flip chip (and other exposed die wafer level) packaging styles, the die may remain exposed. One approach to protecting the die from undesirable light penetration is to apply an optically opaque backcoat layer to the die. U.S. Pat. No. 6,023,094 which is incorporated herein by reference describes methods of applying backcoatings at the wafer level. The described backcoat layer can also have a number of other advantages, including reducing the probability of chipping during wafer sawing operations which can increase wafer yields.
In the semiconductor industry, there are continuing efforts to increase device yield per wafer or lot and reduce the costs and time associated with semiconductor fabrication and packaging. The present invention seeks to provide more efficient approaches to applying a backcoating layer at the wafer level.